[hal-01100778] Fences in weak memory models (extended version)

We present a class of relaxed memory models, defined in Coq, parame-terised by the chosen permitted local reorderings of reads and writes, and by the visibility of inter-and intra-processor communications through memory (e.g. store atomicity relaxation). We prove results on the required behaviour and placement of memory fences to restore a given model (such as Sequential Consistency) from a weaker one. Based on this class of models we develop a tool, diy, that system-atically and automatically generates and runs litmus tests. These tests can be used to explore the behaviour of processor implementations and the behaviour of models, and hence to compare the two against each other. We detail the results of experiments on Power and a model we base on them.



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