[hal-01078142] Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

Multimedia applications and embedded plat-forms are both becoming very complex in order to im-prove user experience Thus multimedia developers need high-level methods to automate time-consuming and error-prone tasks Dynamic dataflow modeling is at-tractive to describe complex applications such as video codecs at a high level of abstraction This paper presents a dataflow-based design approach to implement video codecs on embedded multi-core platforms First we in-troduce a custom architecture model to design low-power multi-core chips based on distributed memory and Transport-Triggered Architecture processor cores Then we describe software synthesis techniques to im-prove dynamic dataflow implementations This method-ology has been implemented into open-source tools and demonstrated on video decoders based on the MPEG-4 Visual standard and the new High Efficiency Video Coding standard The simulations achieve real-time de-coding 40FPS of high definition 720P MPEG-4 Vi-sual video sequences on a custom multi-core platform clocked at 1Ghz which is an improvement of more than 100% over previously proposed implementations



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